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*Mealy State Machine Design `timescale 1ns/1ns module MealyStateM(Reset, Ck, X, OC, outState, Z); input Reset, Ck, X; input OC; //output buffer control output Z; wire Z; output [1:0] outState; wire [1:0] outState; localparam [1:0] S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11; reg [1:0] preState, nextState; always @ (posedge Ck) //State Register begin //sequential if (Reset) //synchronous reset preState

*Modeling a sequential machine: 3 approaches *Modeling a sequential machine: 1) Behavioral modeling - ex.1 //This is a behavioral model of Mealy state machine(Figure 2-51)based on its state table. //The output(Z) and next state are computed before the active edge of the clock. //The state change occurs on the rising edge of the clock. module Code_Converter(X, CLK, Z); input X, CLK, Reset; output..

Any circuit or device can be represented in multiple forms of abstraction. 3 Models: - Behavioral (가장 상위 레벨) : Specifies only the behavior at a higher level of abstraction. Does not imply any particular structure of technology. => 동작 기반 묘사단계 - Data Flow(Register Transfer Level) : Data path and control signals are specified. System is described in terms of the data transfer between registers. => ..

*Finite State Machine Finite State Machine (FSM) is abstract model of describing sequential circuit. *Finite State Machine - Moore, Mealy Machine *MooreState Design `timescale 1ns/1ns module MooreStateM(Reset, Ck, X, OC, outState, Z); //OC, outState는 설계 확인용이고 실제 설계시 필요 없다. input Reset, Ck, X; input OC; output Z; reg Z; output [1:0] outState; wire [1:0] outState; lacalparam [1:0]S0 = 2'b00, S1 = ..

*4bit Counter design `timescale 1ns/1ns module Counter4(Reset, Ck, Mode, Din, Out); input Reset, Ck; input [1:0]Mode; input [3:0]Din; output [3:0]Out; wire [3:0]Out; parameter LOAD = 2'b01, C_UP = 2'b10, C_DOWN = 2'b11; reg [3:0]Register; always@(posedge Ck) //synchronous begin if(Reset) Register

*Shift Register `timescale 1ns/1ns module ShiftRegister(Reset, Ck, Shift, SI, Q); input Reset, Ck, Shift, SI; output [3:0]Q; //4bit출력 reg [3:0]Q; always@(posedge Ck) begin if(Reset)//Synchronous Reset Q

`timescale 1ns/1ns module D_FF(Reset, Ck, Load, D, Q); input Reset, Ck, Load, D; output Q; reg Q; always@(posedge Ck) begin if(Reset) Q

* "If", "Case" Statement An if statement has the form: if (condition) statements 1 else if (condition) statements 2 ... else statements 3 A Case Statement has the form: case expression choice1 : statements1 choice2 : statements2 ... [default : statements5] endcase *Verilog Models for Multiplexers A multiplexer is a conbinational circuit and can be modeled using: - A conditional operator with ass..

*Simple Synthesis Examples 1 In order for code to synthesize correctly, certain conversions must be followed. Even if Verilog code gives the correct result when simulated, it may nor result in hardware that work correctly when synthesized. Sensitivity list에 B가 빠져있다. : always@(A or B) 또는 always@(*)로 수정해야 한다. *Simple Synthesis Examples 2 sequential logic을 사용하였기에 (=>) CLK을 두번 지난다. //always block 수정..

*Compliation, Simulation, and Synthesis of Verilog Code Simulation and synthesis process: - A netlist a list of required components and their interconnections. *Summary *Verilog Data Types and Operators Two main groups of data types: Variable: - An abstraction of a data storage element. - Stores a value from one assignment to the next. An assignment statement in a procedure acts as a trigger tha..

*Multiplexer Design - Conditional Expression A conditional(if 구문) signal assignment statement has the form : assign signal_name = condition ? expression_T : expression_F; if else => 한줄로 mux를 design할 수 있다. `timescale 1ns/1ns module Mux(X, Y, A, Z); input[3:0] X, Y; intput A; output[3:0]Z; assign Z = (A) ? Y : X; //A=1(true)이면 Y를 추출, A = 0(false)이면 X를 추출한다 endmodule *2-to-1 Multiplexer Design(Test..

*Full Adder Design Using Verilog 2023.10.04 - [Study/Digital System Design and Lab] - #1-1 Design a full adder #1-1 Design a full adder *Full Adder *Full Adder Design Using Verilog FullAdder.v file `timescale 1ns/100ps module FullAdder (input x, y, Cin, output Cout, Sum); assign Sum = x ^ y ^ Cin; assign Cout = (x & y) | (x & Cin) | (y & Cin); endmodule timescale 1ns/100ps : time 프리시 jgewjsrhdms..

*Verilog Description of Combinational Circuits A signal assignment statement has the form : Assign [#delay] signal_name = expression; (square brackets indicate that #delay is optional) Concurrent statements (continuous assignments) examples 1-2 assign의 순서가 바뀌어도 다른 Hardware이 설계되진 않는다. (순서중요X) assign #10 A = ~A //A를 10ns 이후 inversion시켜라 => state를 바꾸는 주기적 신호 Q. A대신 CLK은 왜 사용 못하는가? A. CLK의 data type..

*Full Adder *Full Adder Design Using Verilog FullAdder.v file `timescale 1ns/100ps module FullAdder (input x, y, Cin, output Cout, Sum); assign Sum = x ^ y ^ Cin; assign Cout = (x & y) | (x & Cin) | (y & Cin); endmodule timescale 1ns/100ps : time 프리시전으로 time step결정, 얼마나 쪼개서 할 것인지 설정 FullAdder : module의 이름 / 순서에 맞게 mapping하기(순서중요) ^ : exclusive OR FullAdderTester.v file `timescale 1ns/100ps modul..

*Digital System Advantage Reproducibility, Reliability, Accuracy, Noise immunity, Flexibility, Easy of integration, etc... => 집적 용이, 저장이 쉬움->유지보수 쉬움 *Hardware Description Languages(HDLs) HDLs can describe a digital system at several different levels. - behavioral and structural HDLs lead naturally to a top-down design methology Two popular HDLs - VHDL and verilog Verilog is a HDL used to describ..