*Simple Synthesis Examples 1
- In order for code to synthesize correctly, certain conversions must be followed.
- Even if Verilog code gives the correct result when simulated, it may nor result in hardware that work correctly when synthesized.
- Sensitivity list에 B가 빠져있다.
: always@(A or B) 또는 always@(*)로 수정해야 한다.
*Simple Synthesis Examples 2
- sequential logic을 사용하였기에 (=>) CLK을 두번 지난다.
//always block 수정 코드
always@(A or B or C or F)
C = A & B; // statement 1
G = C | F; // statement 2
end
*Simple Synthesis Examples 3
- Considering the code below, why does this code not represent an AND gate with G and D as inputs?
*Simple Synthesis Examples 4
