공대생 말하는 고구마

*Verilog Description of Combinational Circuits A signal assignment statement has the form : Assign [#delay] signal_name = expression; (square brackets indicate that #delay is optional) Concurrent statements (continuous assignments) examples 1-2 assign의 순서가 바뀌어도 다른 Hardware이 설계되진 않는다. (순서중요X) assign #10 A = ~A //A를 10ns 이후 inversion시켜라 => state를 바꾸는 주기적 신호 Q. A대신 CLK은 왜 사용 못하는가? A. CLK의 data type..

*Full Adder *Full Adder Design Using Verilog FullAdder.v file `timescale 1ns/100ps module FullAdder (input x, y, Cin, output Cout, Sum); assign Sum = x ^ y ^ Cin; assign Cout = (x & y) | (x & Cin) | (y & Cin); endmodule timescale 1ns/100ps : time 프리시전으로 time step결정, 얼마나 쪼개서 할 것인지 설정 FullAdder : module의 이름 / 순서에 맞게 mapping하기(순서중요) ^ : exclusive OR FullAdderTester.v file `timescale 1ns/100ps modul..

*Digital System Advantage Reproducibility, Reliability, Accuracy, Noise immunity, Flexibility, Easy of integration, etc... => 집적 용이, 저장이 쉬움->유지보수 쉬움 *Hardware Description Languages(HDLs) HDLs can describe a digital system at several different levels. - behavioral and structural HDLs lead naturally to a top-down design methology Two popular HDLs - VHDL and verilog Verilog is a HDL used to describ..