#2-1 Design a 4-Bit Adder

*Full Adder Design Using Verilog

2023.10.04 - [Study/Digital System Design and Lab] - #1-1 Design a full adder

#1-1 Design a full adder

 

*4-bit Adder Design(Structural Description)

//Structural Description of a 4-Bit Adder

module Adder4 (S, Co, A, B, Ci);
output [3:0] S;
output Co;
intput [3:0] A, B;
input Ci;

wire [3:1] C; // C is internal signal

// instantiate four copies of the FullAdder

FullAdder FA0 (A[0], B[0], Ci, C[1], S[0]);
FullAdder FA1 (A[1], B[1], C[1], C[2], S[1]);
FullAdder FA2 (A[2], B[2], C[2], C[3], S[2]);
FullAdder FA3 (A[3], B[3], C[3], Co, S[3]);

endmodule

 

*4-bit Adder Design(TestBench)

`timescale 1ns/100ps

module Adder4Tester;
reg[3:0] x = 4'b0; //input
reg[3:0] y = 4'b0; //input
reg Cin = 0; //input

wire[3:0] Sum; //output
wire Cout; //output
parameter tlimit = 100;

Adder4 A4 (Sum, Cout, x, y, Cin);

always begin
	if ($time >= tlimit)$stop;
    else begin
    	x = 5;
        repeat(12)#10 y = y+2; //12번 반복하고 10초마다 y값에 2를 더하라
    end
end

integer result;
wire on;

assign on = ($time < tlimit-1)? 1 : 0;

always@(x, y, Cin)  begin
	if(on)begin
    	result = $fopen("result_4bit_Adder.txt");
        $fdisplay(result, $time, ", %d, %d, %d, %d, %d", x, y, Cin, Sum, Cout);
    end
    else
    	$fclose(result);
end

endmodule

 

*4-bit Adder Design - Result(Wave)

 

*4-bit Adder Design - Result(text file)