#3-2 Shift Register

*Shift Register

`timescale 1ns/1ns

module ShiftRegister(Reset, Ck, Shift, SI, Q);
input Reset, Ck, Shift, SI;
output [3:0]Q; //4bit출력
reg [3:0]Q;

always@(posedge Ck)
begin
	if(Reset)//Synchronous Reset
   		Q <= 4'b0000; 
    else if (Shift) //Shift right
    	Q <= {SI, Q[3:1]};
    else Q <= Q;
end

endmodule

shift right

 

*Shift Register TB

`timescale

module ShiftRegister_Tb;

parameter tlimit = 100;
parameter ckPeriod = 7;

reg Reset = 1'b1, Ck = 1'b0, Shift = 1'b0, SI = 1'b0;
wire [3:0]Q;

ShiftRegister U1 (Reset, Ck, Shift, SI, Q);

initial
begin
	#25 Reset = 1'b0;
    #5 Shift = 1'b1; SI = 1'b1;
    #28 SI = 1'b0;
    #14 SI = 1'b1;
    #14 Shift = 1'b0;
end

always #ckPeriod Ck = ~Ck; //14ns의 주기를 갖는다.

integer result;

always@(negedge Ck)
begin
	if($time >= tlimit)$stop
    else begin
    result = $fopen("result.txt");
    $display(result, "time = %d, Reset = %d, Shift = %d, SI = %d, Q = %d", $time, Reset, Shift, SI, Q);
    end
end

endmodule

=> 헷갈렸던 개념 : reg와 wire
: 쉽게 생각하면 assign을 쓰는 data type은 wire사용하고 always나 initial에서 쓰는 data type은 reg라 생각하기

 

*Shift Register - Result

 

*Shift Register - Result(Waveform)

 

*Exercise 

• By instantiating four D-FFs, design the shift-right register

2023.10.15 - [Study/Digital System Design and Lab] - #3-1 D Flip-Flop

//D_FF
`timescale 1ns/1ns

module D_FF(Reset, Ck, Load, D, Q);
input Reset, Ck, Load, D;
output Q;
reg Q;

always@(posedge Ck) 
begin
	if(Reset) Q <= 1'b0; //synchronous reset
    else if(Load) Q <= D;
    else Q <= Q;
end

endmodule

`timescale 1ns/1ns

module ShiftRegisterST(Reset, Ck, Shift, SI, Q);
input Reset, Ck, Shift, SI;
output [3:0]Q; //4bit출력
wire [3:0]Q;

D_FF U3(Reset, CK, Shift, SI, Q[3]);
D_FF U2(Reset, Ck, Shift, Q[3], Q[2]);
D_FF U1(Reset, Ck, Shift, Q[2], Q[1]);
D_FF U0(Reset, Ck, Shift, Q[1], Q[0]);

endmodule

//ShiftRegister_Tb_D_FF
`timescale 1ns/1ns

module ShiftRegister_Tb;

parameter tlimit = 100;
parameter ckPeriod = 7;

reg Reset = 1'b1, Ck = 1'b0, Shift = 1'b0, SI = 1'b0;
wire [3:0]Q;

ShiftRegisterST U1 (Reset, Ck, Shift, SI, Q);

initial
begin
	#25 Reset = 1'b0;
    #5 Shift = 1'b1; SI = 1'b1;
    #28 SI = 1'b0;
    #14 SI = 1'b1;
    #14 Shift = 1'b0;
end

always #ckPeriod Ck = ~Ck; //14ns의 주기를 갖는다.

integer result;

always@(negedge Ck)
begin
	if($time >= tlimit)$stop
    else begin
    result = $fopen("result_EX.txt");
    $display(result, "time = %d, Reset = %d, Shift = %d, SI = %d, Q = %d", $time, Reset, Shift, SI, Q);
    end
end

endmodule